1. Field of the Invention
The present invention generally relates to a testing and design verification of computer hardware devices and more specifically to the testing of the integrity of the contents of registers during the course of operation of a device.
2. Description of the Related Art
Hardware devices such as Central Processing Units (CPU) contain special high speed memory areas referred to as registers. Registers can be used for manipulating data and for storing important information that determines the functionality of the device based on the specifications of the hardware environment in which it is placed. For example, certain bits in a given register may set one among many connection speeds between the hardware device and another device. Such registers are called configuration registers. During the course of normal operation of the hardware device, configuration registers and other registers may be accessed several times and by many different devices.
As an example, in a gaming system, a graphical processing unit (GPU) and/or direct memory access (DMA) unit may access registers of a CPU, and vice-versa. It is therefore essential to ensure that values in these registers are not changed inadvertently during these accesses. Further, the values in all registers must maintain their integrity during access to a particular register itself, accesses to any other registers and during non-register traffic.
The goal of testing and design verification procedures is to ensure that the default values in the configuration registers are not changed and that all registers contain only intended values. This typically involves developing test cases to simulate accesses to a device during normal operation. FIG. 1 illustrates an exemplary simulation environment 100, in which a tester 102 may include a processor 108 configured to access registers 122 of a Device Under Test (DUT) 120 as part of a test procedure.
Conventionally, test cases must be manually developed based on the Hardware Specification 110 of DUT 120. A manual test case contains a sequence of device access instructions which can include a series of read and write operations to the registers. Several, different manual test cases may be developed to encapsulate different circumstances. However, each manual test case must be run independently. Register values are verified during the test by comparing values read from the registers to expected values or values previously written to the registers.
One problem with using manual test cases lies in its deterministic nature. Register accesses by manual test cases are performed in a given sequence using the same write data every time a particular manual test case is run. However, the manual test cases may not closely simulate real operating conditions, as accesses to hardware devices during normal operation are not so deterministic. To capture the many different ways in which a hardware device can be accessed would require the development of just as many manual test cases, which may prove impractical. As a result, many design problems such as interdependencies between registers that result in erroneous register values may not be discovered.
Therefore, there is a need for a simulation environment that better simulates the accesses to a hardware device during normal operation for more effective testing and design verification.